(a) Field of the Invention
The present disclosure relates to a thin film transistor array panel and a manufacturing method thereof. More particularly, the disclosure relates to a thin film transistor array panel and a manufacturing method thereof that prevents a disconnection of wiring due to misalignment of a mask, and that simplifies and reduces the cost of a process by reducing the number of masks.
(b) Description of the Related Art
A thin film transistor is generally used as a switching element to independently drive a pixel in a flat display device such as a liquid crystal display or an organic light emitting device. The thin film transistor array panel includes a thin film transistor, a pixel electrode that is connected thereto, a gate line that transmits a gate signal to the thin film transistor, and a data line that transmits a data signal.
The thin film transistor includes a gate electrode that is connected to the gate line, a source electrode that is connected to the data line, a drain electrode that is connected to the pixel electrode, and a semiconductor layer that is disposed on the gate electrode between the source electrode and drain electrode, and the data signal is transmitted to the pixel electrode from the data line according to the gate signal from the gate line.
The thin film transistor array panel is formed by performing a plurality of photo and etching processes after forming a metal layer on a substrate and aligning a mask. After a photo and etching process is performed for aligning a first mask on the substrate, the photo and etching process is similarly performed for aligning a second mask. When the second mask and the first mask are misaligned, a desired pattern may not be obtained.
For example, a process of forming a contact hole exposing the semiconductor layer by using the first mask to form a source electrode and a drain electrode connected to a semiconductor layer and forming the source electrode and the drain electrode connected to the semiconductor layer through the contact hole by using the second mask may be performed. When the second mask is misaligned from the first mask, the source electrode and the drain electrode are only formed in a partial region inside the contact hole such that the semiconductor layer is not normally connected.
The above information disclosed in this Background section is only for enhancement of understanding of background information and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.